SR. RFIC - PLL DESIGN ENGINEER
Company: Apple
Location: San Diego
Posted on: October 2, 2024
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Job Description:
SummaryPosted: Role Number:200539415Would you like to join
Apple's growing wireless silicon development team? The wireless
RFIC team architects, designs, and validates radio transceivers
integrated into complex wireless SoCs. Our wireless organization is
responsible for all aspects of wireless silicon development that
transform the user experience at the product level, all of which is
driven by a best-in-class vertically integrated engineering team
spanning RF/Analog architecture and design, Systems/PHY/MAC
architecture and design, VLSI/RTL design and integration,
Emulation, Design Verification, Test and Validation, and FW/SW
engineering.As Sr. RFIC - PLL Design Engineer within the Wireless
Radio team, you will be at the center of a wireless SoC design
group with a critical impact on getting Apple's state-of-the-art
wireless connectivity solutions into hundreds of millions of
products.DescriptionAs a Senior RFIC-PLL Designer, you are going to
be responsible for providing analog and digital PLL solutions for
wireless SoC and driving them to mass production for Apple's
Wireless Connectivity products. Responsibilities include:- Lead
design of radio transceiver chains including analog PLLs - VCOs,
digital PLLs - DCOs, LOGen, and chain of blocks in RX and TX for
wireless connectivity products. - Drive radio KPI (power, area,
performance) to meet product requirements- Work with
cross-functional teams including platform architecture, wireless
design, RF HW and SW to define radio features enabling wireless
innovation.- Work closely with RF Systems in block level and high
level specifications of the PLL-LOGen, TX and RX line ups, and
proper distribution of spec margins in the chain. - Hands-on design
contributions starting from concept, architecture and topology to
transistor-level feasibility studies and KPI trade-off analysis to
actual design, simulations and extractions. - Design of RF and
Analog loopbacks for calibration and compensation. - Work through
Co-Existence scenarios and design to meet the CoEx requirements. -
Oversee the floorplan layout and verification of the design to
ensure a successful tape-out. - Close collaboration with RFIC test
engineers in the bring up, debug and optimization of the wireless
connectivity chip through the productization.- Provide design
versus silicon measurements correlation, and compliance with
specification for a volume production.Key QualificationsTypically
requires 10+ years of RF/analog and mixed-signal design experience
in cutting-edge RF CMOS design.Direct experience in designing and
bringing into mass production of wireless transceivers in deep
sub-micron RFCMOS technology.Experienced in design and development
of fractional N Synthesizers, Digital PLLs, Analog PLLs, LO-Gen for
high performance application and also low power application.Hands
on experience in designing TDC, GRO, Digital Filters, Sigma Delta
Modulators, Pre-scalers and MMD, DCOs, PFD-CP, and VCOs. Modeling,
analysis and design of SD noise cancellation and spur cancellation
techniques.Deep understanding of analog, mixed-signal and RF
circuit design. This includes LNAs, PAs, mixers, baseband filters,
VGAs and calibration methods associated with high performance
wireless systems.Familiarity with various RF transceiver
architectures and their trade-offs, system specifications and
ability to work with system architects to translate system
requirements into circuit requirements at IC level.Experienced in
Cadence Virtuoso, Spectre RF, Matlab, EM simulation (EMX, HFSS) and
similar tools.Familiarity with mixed-signal mode verification
methodology (SystemVerilog, AMS, Nanotime).Demonstrated capability
to work with digital design group for an optimum partition between
digital and analog domain, timing requirements.Extensive experience
in fractional N synthesizer and LOGen silicon characterization and
debug.Education & ExperienceBS and 10+ years of relevant industry
experience. MSEE and PhD is preferred.Additional RequirementsApple
is an equal opportunity employer that is committed to inclusion and
diversity. We also take affirmative action to offer employment and
advancement opportunities to all applicants, including minorities,
women, protected veterans, and individuals with disabilities. Apple
will not discriminate or retaliate against applicants who inquire
about, disclose, or discuss their compensation or that of other
applicants.Pay & BenefitsAt Apple, base pay is one part of our
total compensation package and is determined within a range. This
provides the opportunity to progress as you grow and develop within
a role. The base pay range for this role is between $166,600 and
$296,300, and your base pay will depend on your skills,
qualifications, experience, and location.Apple employees also have
the opportunity to become an Apple shareholder through
participation in Apple's discretionary employee stock programs.
Apple employees are eligible for discretionary restricted stock
unit awards, and can purchase Apple stock at a discount if
voluntarily participating in Apple's Employee Stock Purchase Plan.
You'll also receive benefits including: Comprehensive medical and
dental coverage, retirement benefits, a range of discounted
products and free services, and for formal education related to
advancing your career at Apple, reimbursement for certain
educational expenses - including tuition. Additionally, this role
might be eligible for discretionary bonuses or commission payments
as well as relocation. Learn more about Apple Benefits.Note: Apple
benefit, compensation and employee stock programs are subject to
eligibility requirements and other terms of the applicable plan or
program.Apple is an equal opportunity employer that is committed to
inclusion and diversity. We take affirmative action to ensure equal
opportunity for all applicants without regard to race, color,
religion, sex, sexual orientation, gender identity, national
origin, disability, Veteran status, or other legally protected
characteristics. Learn more about your EEO rights as an
applicant.
Keywords: Apple, Santee , SR. RFIC - PLL DESIGN ENGINEER, Engineering , San Diego, California
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